The present invention relates to electronic circuits, and more particularly, to techniques for generating periodic signals having fractional frequencies.
New applications such as peer-to-peer sharing, social networking, digital video transmission, broadband wireless handsets and video conferencing and messaging have driven a need for data transport systems that have a larger bandwidth. With the introduction and adoption of 40-/100-Gbit (Gigabit) Ethernet, and the acceptance of optical transport network (OTN) standards, service providers are now turning to 100-Gbit OTN solutions to scale their channel capacity by a factor of ten.
However, there are a large number of legacy SONET, Ethernet, and storage systems operating at lower data rates, which somehow must be connected into the emerging OTN infrastructure. One way to connect the OTN infrastructure with the legacy systems that maximizes the available bandwidth while reducing space and power, is to aggregate multiple lower data-rate client channels onto a single wavelength at a higher data rate using a 100-Gbit OTN multiplexing transponder (muxponder).
FIG. 1 illustrates an example of a prior art transmission system having transponders 101-102. Transponder 101 functions as a multiplexing transponder 101 in the transmission system of FIG. 1, and transponder 102 functions as a demultiplexing transponder in the transmission system of FIG. 1. Multiplexing transponder 101 receives an N number of input client signals I1-IN (e.g., 16) that comprise data. Client signals I1-IN have different data rates and are generated according to different data transmission protocols. The data rates of client signals I1-IN are less than 100 Gigabits per second (Gbps). Multiplexing transponder 101 combines client signals I1-IN into a single high speed 100 Gbps data stream TS that is transmitted through OTN 103 to demultiplexing transponder 102. Demultiplexing transponder 102 separates data stream TS into an N number of lower speed output data signals O1-ON (e.g., 16). Output data signals O1-ON correspond to input client signals I1-IN, respectively.
FIG. 2 illustrates details of demultiplexing transponder 102 shown in FIG. 1. Demultiplexing transponder 102 includes demultiplexer 201, an N number of first-in-first-out (FIFO) buffers including FIFO buffers 202 and 212, an N number of controllers including controllers 203 and 213, an N number of soft intellectual property (IP) circuits including soft IP circuits 204 and 214, an N number of serializer/deserializer (SerDes) circuits including SerDes circuits 205 and 215, and an N number of transmitter phase-locked loop (TxPLL) circuits including TxPLL circuits 206 and 216. Demultiplexing transponder 102 is connected to an N number of external voltage-controlled crystal oscillator (VCXO) circuits including VCXO circuits 207 and 217. Transponder 102 is in an integrated circuit. The VCXO circuits are not in the integrated circuit that includes transponder 102.
Demultiplexer 201 separates data stream TS into an N number of data streams P1-PN. FIFO buffers 202 and 212 store the data signals in data streams P1 and PN, respectively. FIFO buffers 202 and 212 output the data signals in parallel as data signals F1 and FN, respectively. Controllers 203 and 213 generate error signals that indicate frequency shifts in the data signals stored in FIFO buffers 202 and 212, respectively. Soft IP circuits 204 and 214 generate digital control signals D1 and DN based on the error signals generated by controllers 203 and 213, respectively.
VCXO circuits 207 and 217 generate reference clock signals R1 and RN that are provided to inputs of TxPLL circuits 206 and 216, respectively. VCXO circuits 207 and 217 vary the frequencies of reference clock signals R1 and RN based on signals D1 and DN indicating frequency shifts in the data signals stored in FIFO buffers 202 and 212, respectively. TxPLL circuits 206 and 216 multiply the frequencies of reference clock signals R1 and RN to generate the frequencies of clock signals C1 and CN, respectively. Serializer circuits in SerDes circuits 205 and 215 convert parallel data signals F1 and FN received from FIFO buffer circuits 202 and 212 into serial output data signals O1 and ON in response to clock signals C1 and CN, respectively.